In recent years, with increasingly finer structures in LSI (Large Scale Integrated circuit) design, design rules applied to semiconductor processes become more complex to prevent deterioration of yields due to finer structures. For example, there has been no design rule concerning the minimum spacing value that defines the minimum interval value to prevent a short circuit between a wiring layer and via layers thereon and thereunder during manufacture of semiconductors. However, with increasingly finer semiconductor structures, a minimum spacing rule between the wiring layer and via layers is sometimes newly added. Here, the via layer is a layer to form a connecting hole called a “via” for the purpose of connecting wiring layers formed vertically.
In recent LSI for CPU, a technology called a body bias technology is applied for the purpose of saving power and improving yields. The body bias technology is a technology to suppress a leakage current during standby, which poses a problem with development of finer structures of process technology, by applying a voltage to a semiconductor substrate in a direction opposite to a normal direction voltage. Since a body bias power supply sometimes has a higher voltage than an ordinary power supply, design rules for high-voltage devices are applied to body bias power supply wires. In contrast to design rules for ordinary voltage devices, design rules for high-voltage devices applied to semiconductor process technology used by the applicants for manufacture of semiconductors need application of spacing rules between a wiring layer and a via layer.
Conventional wiring tools consider only spacing rules between wiring layers or between via layers and do not consider spacing rules between a wiring layer and a via layer. In the past, high-voltage devices were present only in an internal area of an IO (Input Output) macro in charge of the input/output function of LSI. Thus, it is possible to define the perimeter of a high-voltage device as a wire protected area and thus, design rules concerning spacing are not applied in the first place even if wiring tools do not consider spacing rules between a wiring layer and a via layer so that spacing rules are not violated.
However, a body bias power supply wire may be present on the whole chip surface and if the perimeter of a high-voltage device is defined as a wire protected area, an area available for wire is significantly reduced, leading to an increased chip area. An increase in chip area leads to an increase in costs and deterioration of yields. By enabling consideration of spacing rules between a wiring layer and a via layer by using wiring tools, an increase in area, that is, an increase in costs and deterioration of yields of a chip to which body bias is applied can be prevented.
Conventional wiring tools consider only minimum spacing rules between wiring layers or between via layers. The operation flow of conventional wiring information generation processing is generally like processing illustrated in FIG. 13. Incidentally, a sequence control processing below is performed while a group of table data illustrated in FIGS. 19A-19L are being stored in a storage device.
A net table (see FIG. 19A) is searched by repeated processing of operations between S1301 and the judgment at S1307 for processing all nets representing connection information of wires in a circuit. At S1302, the net type (see FIG. 19A) is verified and processing of S1303 to S1306 is performed if the net being processed has a net type to be wired. At S1303, as creation processing of a wire protected area, a wire protected area that takes spacing rules in the same layer into consideration is created for a terminal figure, obstacle figure, wire, or via figure. At S1304, a pathway that connects terminal figures belonging to the net being processed is searched for by a route searching algorithm in such a way that the wire protected areas set at S1303 are avoided. At S1305, wires and vias are registered according to route searching results in a wire table (see FIG. 19C and a via table (see FIG. 19D) respectively. At S1306, after wires are set to the pathway, all wire protected areas registered in a wire protected area table (see FIG. 19E) are deleted. At S1307, control returns to S1301 if there is any unprocessed net.
In control operations illustrated by an operation flowchart in FIG. 13, details of creation processing of a wire protected area at S1303 is illustrated by an operation flowchart in FIG. 14. A logic element device table (see FIG. 19B) is searched by repeated processing of S1402 and S1403 operations between S1401 and the judgment at S1404 for processing all logic element devices.
At S1402, wire protected areas are created for terminal figures held by a logic element device. A terminal is a circuit component that connects wires. At S1403, wire protected areas are created for obstacle figures held by a logic element device. An obstacle figure is a figure portion that is constructed inside a logic element device and in which it is preferable to prohibit wiring and is a wire protected area inside a logic element device. At S1404, control returns to S1401 if there is any unprocessed logic element device.
Subsequently, the net table (see FIG. 19A) is searched by repeated processing of operations of S1406 to S1408 between S1405 and the judgment at S1409 for processing all nets. At S1406, only nets excluding those being wired are selected. At S1407, wire protected areas for existing wires for a net are created. At S1408, wire protected areas for existing via figures for a net are created. At S1409, control returns to S1405 if there is any unprocessed net.
In control operations illustrated by the operation flowchart in FIG. 14, a control operation of creating wire protected areas for terminal figures held by the logic element device at S1402 is illustrated by an operation flowchart in FIG. 15. A terminal table (see FIG. 19F) is searched by repeated processing of operations S1502 to S1508 between S1501 and the judgment at S1509 for processing all terminals. At S1502, only nets that are not being wired are selected. A terminal figure table (see FIG. 19G) held by a terminal is searched by repeated processing of S1503 to 1507 operations between S1502 and the judgment at S1508 for processing all terminal figures held by one terminal. At S1504, a layer table (see FIG. 19H) is searched to acquire a layer having the layer number of the terminal figure being processed. At S1505, an X-axis direction size and a Y-axis direction size are calculated from lower left vertex coordinates and upper right vertex coordinates (see FIG. 19G) of the terminal figure being processed to decide a smaller value as the width.
At S1506, a registered entry in which the minimum width and maximum width satisfying the following condition, is searched for from a spacing table (see FIG. 19I) pointed to by a spacing pointer (see FIG. 19H) held by the layer acquired at S1504. Then, the spacing value registered in the searched entry is acquired.Condition: Minimum width≦width decided at S1505≦maximum width
The spacing value represents a horizontal distance between one wire among a plurality of wires and another wire when the semiconductor substrate is assumed to be in a horizontal plane. At S1507, a wire protected area is registered in the wire protected area table (see FIG. 19E). In the table, the layer number (see FIG. 19G) of the terminal figure being processed is set as the layer number. In the table, lower left vertex coordinates and upper right vertex coordinates of a figure obtained by extending the lower left vertex coordinates and upper right vertex coordinates (see FIG. 19G) of the terminal figure being processed by the spacing value acquired at S1506 vertically and horizontally are set as the lower left vertex coordinates and upper right vertex coordinates. Accordingly, in the wiring layer in which the terminal figure is present, a wire protected area will be set for the terminal figure and the range corresponding to the spacing value therearound.
At S1508, control returns to S1503 if there is any unprocessed terminal figure. After processing for all terminal figures held by one terminal is completed by processing S1503 to S1508, a judgment at S1509 is made and control returns to S1501 if there is any unprocessed terminal.
In control operations illustrated by the operation flowchart in FIG. 14, a control operation of creating wire protected areas for obstacle figures held by the logic element device at S1403 is illustrated by an operation flowchart in FIG. 16. An obstacle figure table (see FIG. 19I) held by the logic element device is searched by repeated processing of operations S1602 to S1606 between S1601 and the judgment at S1607 for processing all obstacle figures. At S1602, the layer table (see FIG. 19H) is searched to acquire a layer having the layer number (see FIG. 19I) of the obstacle figure being processed. At S1603, if the layer type of the layer acquired at S1602 is a wiring layer, processing at the next S1604 is performed.
At S1604, the X-axis direction size and the Y-axis direction size are calculated from lower left vertex coordinates and upper right vertex coordinates (see FIG. 19I) of the obstacle figure being processed to decide a smaller value as the width.
At S1605, if the layer type of the layer acquired at S1602 is a wiring layer, a registered entry in which the minimum width and maximum width satisfying the following condition, is searched for from the spacing table (see FIG. 19I) pointed to by the spacing pointer (see FIG. 19H) held by the layer acquired at S1602. Then, the spacing value registered in the searched entry is acquired.Condition: Minimum width≦width decided at step S1604≦maximum width
If the layer type of the layer acquired at S1602 is a via layer, instead of a wiring layer, the spacing value in the spacing table (see FIG. 19I) pointed to by the spacing pointer (see FIG. 19H) held by the layer acquired at S1602 is acquired.
At S1606, a wire protected area is registered in the wire protected area table (see FIG. 19E). In the table, the layer number (see FIG. 19I) of the obstacle figure being processed is set as the layer number. In the table, lower left vertex coordinates and upper right vertex coordinates of a figure obtained by extending the lower left vertex coordinates and upper right vertex coordinates (see FIG. 19J) of the obstacle figure being processed by the spacing value acquired at S1605 vertically and horizontally are set as the lower left vertex coordinates and upper right vertex coordinates. Accordingly, in the wiring layer or via layer in which the obstacle figure is present, a wire protected area will be set for the obstacle figure and the range corresponding to the spacing value therearound.
At S1607, control returns to S1601 if there is any unprocessed obstacle figure.
In control operations illustrated by the operation flowchart in FIG. 14, a control operation of creating wire protected areas for wires for the net at S1407 is illustrated by an operation flowchart, in FIG. 17. The wire table (see FIG. 19C) for the net is searched by repeated processing of operations S1702 to S1705 between S1701 and the judgment at S1706 for processing all wires.
At S1702, the layer table (see FIG. 19H) is searched to acquire a layer having the layer number (see FIG. 19C) of the wire being processed. At S1703, the wire width (see FIG. 19C) of the wire being processed is acquired. At S1704, a registered entry in which the minimum width and maximum width satisfying the following condition, is searched for from the spacing table (see FIG. 19I) pointed to by the spacing pointer (see FIG. 19H) held by the layer acquired at S1702. Then, the spacing value registered in the searched entry is acquired.Condition: Minimum width≦wire width acquired at step S1703≦maximum width
At S1705, a wire protected area is registered in the wire protected area table (see FIG. 19E). In the table, the layer number (see FIG. 19C) of the wire being processed is set as the layer number. In the table, as lower left vertex coordinates and upper right vertex coordinates, an inclusion rectangle of the wire is calculated from start point coordinates, end point coordinates, and the wire width (see FIG. 19C) of the wire being processed. Then, lower left vertex coordinates and upper right vertex coordinates of a figure obtained by extending the lower left vertex coordinates and upper right vertex coordinates of the calculated inclusion rectangle by the spacing value acquired at S1704 are set. Accordingly, a wire protected area will be set in the wiring layer for a rectangle area corresponding to the wire and the range corresponding to the spacing value therearound.
At S1706, control returns to S1701 if there is any unprocessed wire.
In control operations illustrated by the operation flowchart in FIG. 14, a control operation of creating wire protected areas for via figures for the net at S1408 is illustrated by an operation flowchart in FIG. 18. The via table (see FIG. 19D) for the net is searched by repeated processing of operation S1802 to S1809 between S1801 and the judgment at S1810 for processing all vias.
At S1802, a via type table (see FIG. 19K) is searched to acquire the via type having the via number (see FIG. 19D) of the via being processed. A via figure table (see FIG. 19L) is searched by a figure table pointer (see FIG. 19K) held by the via type acquired at S1802 by repeated processing of operations S1803 to S1808 between S1802 and the judgment at S1809. Then, processing of S1803 to S1808 is performed for all via figures held by the via type.
At S1804, the layer table (see FIG. 19H) is searched to acquire a layer having the layer number (see FIG. 19L) of the via figure being processed. At S1805, if the layer type of the layer acquired at S1804 is a wiring layer, processing at the next S1806 is performed. At S1806, the X-axis direction size and the Y-axis direction size are calculated from lower left vertex coordinates and upper right vertex coordinates (see FIG. 19L) of the via figure being processed to decide a smaller value as the width.
At S1807, if the layer type of the layer acquired at S1804 is a wiring layer, a registered entry in which the minimum width and maximum width satisfying the following condition, is searched for from the spacing table (see FIG. 19I) pointed to by the spacing pointer (see FIG. 19H) held by the layer acquired at S1804. Then, the spacing value registered in the searched entry is acquired.Condition: Minimum width≦width decided at S1806≦maximum width
If the layer type of the layer acquired at S1804 is a via layer, instead of a wiring layer, the spacing value (see FIG. 19H) in the entry of the layer table corresponding to the layer acquired at S1804 is acquired.
At S1808, a wire protected area is registered in the wire protected area table (see FIG. 19E). In the table, the layer number (see FIG. 19L) of the via figure being processed is set as the layer number. In the table, lower left vertex coordinates and upper right vertex coordinates of a figure obtained by extending the lower left vertex coordinates and upper right vertex coordinates (see FIG. 19L) of the via figure being processed by the spacing value acquired at S1807 vertically and horizontally and adding values of origin coordinates (see FIG. 19D) of the via being processed are set as the lower left vertex coordinates and upper right vertex coordinates. Accordingly, in the wiring layer or via layer, a wire protected area will be set for the via figure and the range corresponding to the spacing value therearound.
At S1809, control returns to S1803 if there is any unprocessed via figure. After processing for all via figures held by one via is completed by processing by S1803 to S1809, a judgment at S1810 is made and control to return to S1801 is exercised if there is any unprocessed via.
Wire protected areas corresponding to circuit components are set as described above and wiring processing based thereon is performed to realize generation of wiring information.